1. Field of the Invention
This invention relates to an imaging or image pick-up device, and more particularly to a solid-state imaging device in which photoelectric conversion elements, etc. are integrated on a semiconductor substrate.
2. Description of the Related Art
The solid-state imaging device is required to have a comparable resolution to that of the image pick-up electronic tube used in the current television broadcasting. Therefore, it is necessary to form on a semiconductor substrate, a picture element (photoelectric conversion element) matrix which includes 500 cells in the vertical (column) direction and 800 to 1000 cells in the horizontal (row) direction, and scanning elements corresponding thereto. Therefore, the solid state imaging device is manufactured by using the MOS LSI technology which is capable of high integration and generally employs the charge coupled device (CCD) or the MOS transistor as the constituent element.
This prior art will be described referring to the drawings, hereinbelow.
FIG. 1 is a circuit diagram showing the conceptual structure of the conventional MOS type solid-state imaging device.
Photoelectric conversion elements are made of photodiodes 1 and disposed regularly in a two-dimensional (matrix) form of the horizontal and the vertical directions. The photodiode stores a signal charge which corresponds to the quantity of incident light. To each of the photodiodes 1, the source side of a vertical switching MOS transistor (vertical MOST) 4 is connected. The gates of the vertical MOST's 4 in one horizontal line (row) are connected to a vertical scan circuit 2 through a vertical gate line 3. The drain sides of the vertical MOST's 4 in one vertical line (column) are connected to a vertical signal line 8. The vertical MOST's are turned on and off by the selection signal supplied from the vertical scan circuit 2. At each one end of the vertical signal lines 8, the source side of a horizontal switch MOST transistor (horizontal MOST) 6 is connected. The gates of the horizontal MOST's 6 are connected to respective gate lines of a horizontal scan circuit. The drain sides of the horizontal MOST's 6 are connected commonly to an external amplifier 7 through a horizontal signal line 9. The horizontal MOST's 6 are turned on and off by the selection signal supplied from a horizontal scan circuit 5.
Hereinbelow, the operation of thin solid-state imaging device will be explained. Firstly, in the horizontal blanking period, the voltage of a vertical gate line 3 of a row selected by the vertical scan circuit 2 rises high to open the vertical switches 4 of the row at the same time. Then, the signal charges are sent from the photodiodes 1 to the vertical signal lines 8. Then, in the horizontal scan period, the horizontal scan circuit 5 operates to successively opens and closes the horizontal switches 6. The signal charges are successively amplified in the external amplifier 7 and outputted through an output terminal 10.
FIG. 2 shows a cross-sectional structure of one picture element comprising a photodiode 1 and a vertical MOST 4. In a semiconductor substrate 11 of a first conductivity type, an impurity dosed region 14 of a second conductivity type (a conductivity type different from that of the semiconductor substrate 11) for forming a photodiode 1 and another impurity dosed region 16 of the second conductivity type for forming the drain of a vertical MOST 4 are disposed. Here, the impurity dosed region 14 also serves as the source of the vertical MOST 4. On the surface of the semiconductor substrate 11, a gate electrode 3' of the vertical MOST 4 is disposed with the interposition of an insulating oxide film 12. A vertical signal line 8 is connected to the impurity dosed region 16 which constitutes the drain.
The solid-state imaging device of this kind has an advantage that integration is relatively easy because of the use of the MOS LSI technology which allows the manufacture of an integrated structure of photoelectric conversion elements and switching elements. For example, JP-A-55-110476 discloses a solid-state imaging device of this kind.
Next, a solid-state imaging device employing an SOI (silicon-on-insulator) structure will be explained. With this respect, reference may be made to IEDM 86, Tech. Dig., pp. 369-372, which is incorporated herein by reference.
This SOI solid-state imaging device has a similar equivalent circuit to the circuit of FIG. 1, but has a different structure of the vertical MOST 4. FIG. 3A shows a cross-sectional structure of one picture element of this SOI solid-state imaging device, in analogy to the structure of FIG. 2. In a semiconductor substrate 11 made of p type silicon, an impurity dosed n+ type region 14 for forming a photodiode is disposed and isolated by a thermal oxide film 12 and a p+ type diffusion layer 17. A vertical MOST comprising a source 19, a drain 20 and a gate 3' extends from this n+ type impurity dosed region 14 onto the thermal oxide film 12. The source 19 is connected to the impurity dosed region 14 at the right end portion thereof through surface contact. The general structure is covered with a passivation film 18. A signal line 8 is connected to the drain 20. Here, since the vertical MOST comprising the source 19, the drain 20 and the gate 3' is formed in an SOI structure, it is possible to reduce the parasitic capacitance between the drain 20 and the p type silicon substrate. Therefore, the parasitic capacitance of the signal line 8 can also be reduced to suppress the output noise level. This is because the square of the output noise current is proportional to the total capacitance of the signal line 8.
FIG. 3B shows a plan lay-out of one picture element shown in FIG. 3A. At the right end of the impurity dosed region 14 for forming a photodiode, the source 19 of a vertical MOST 4 of an SOI structure is connected. This SOI structure further constitutes a vertical MOST comprising a source 19, a drain 20 and a gate 3', outside of the impurity dosed region 14 for forming the photodiode.
As FIG. 3B shows a plan lay-out of an SOI solid-state imaging device, the MOST type solid-state imaging device of FIG. 2 may be considered to have a similar plan lay-out.
As is apparent from the cross-sections of FIGS. 2 and 3A and the plan lay-out of FIG. 3B, according to the conventional art, the vertical MOST for reading out the signal charge is provided near but separately from the impurity dosed region for forming the photodiode. Therefore, letting the area occupation ratio of this vertical MOST per one picture element be about 10%, the area of about 10% in total does not contribute to photoelectric conversion. The impurity dosed region for forming the photodiode requires a certain occupation area for providing a predetermined signal-to-noise (S/N) ratio. For increasing the resolution of the solid-state imaging device, it is necessary to reduce the occupation area of one picture element as far as possible. According to the conventional art as explained above, however, there exists a certain limit in the occupation area per one picture element. Thus, there is a problem that high resolution cannot be realized.